Display device including roll and crawl capabilities

ABSTRACT

Data display apparatus is provided with the capability for moving the lines of data vertically upward across the face of the display tube, or characters of data from right to left across the face of the display tube. Characters stored in a memory are read out by addressing the memory in synchronism with a TV display scan.

IJIIII States Inventor Appl. No. Filed Patented Assignee aterII DISPLAYDEVICE INCLUDING ROLL AND CIRAWL CAPABILITIES 27 Claims, 21 DrawingFigs.

US. Cl 340/324 A, 3 15/22 [56] References Cited UNITED STATES PATENTS3,406,387 10/1968 Werme 340/324 A 3,422,420 1/1969 Clark 340/324 APrimary ExaminerJohn W. Caldwell Assistant Examiner-David L. TraftomAttorneys-Samuel Lindenberg and Arthur Freilich COMP $YNC, HOTZ1Z SYNC,EXTERNAL syNc I SYNC. COMP $PARATOR VERT svNc. 57

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PATENTEUULI 'I9I97I 3,61%766 sum cm 13 \O COMPARATOR '70 TO COMPARATOR\62 aflo ADDRESS GEN. (Ha Efl'O ADDREss CQEH Hag T/L J M VV WI W2 W2 W8W5 Bl Bl B2 B2 B 6 BIS NH H26 NH H24 mam/w D\5PLAY V14 UNE 00 CHARACTERCOUNTER (,CDUNTER (.LARSOK A ON /OFF AMT 1 T I \6 CURSOR 2 \64 h TCURSOR X XCOUNTER CURSOR (REVERSBLE COMPAR 1 w (.URSOR DOWN CURSOR Y yCOU NTER fig C REVE R sx E'JLE \6 COMPARATOR ee CURSOR HOME FROM CU RgoRCOUNTER 26 f1? 7 INVENTOR. JAMES M. K/EV/T M&M

ATTORNEYS PATENTEBum 19ml 3,81 41,766

sum DSBF 13 I 5 SOURCE To MEMORY INVENTOR. JAMES M K/EV/T MLI WATTOR/VEXS PATENTEDU 191971 36 1 40766 SHEH 06 0F m SLOW ROLL KEYSLOWCRAWL KEY FAST Rou.

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DISPLAY DEVICE INCLUDING ROlLlL AND CRAWIL CAPABILITIES BACKGROUND OFTHE INVENTION functions at frequencies such as those used in hometelevision 1 receivers, and displays data, which is entered into thissystem, either by means of a keyboard or tape, which are received over awire. The display system has a storage facility into which the incomingdata is entered. The data is thereafter read out, decoded, convertedinto signals which can be displayed and thereafter displayed.

This invention relates to display apparatus which functions to producethe appearance of lines of data being displayed moving upward from thebottom towards the top of a display tube. Apparatus is also provided forproducing the effect of characters of being displayed, the data movingin lines from the right to the left across the face of the display tube.

A feature of this invention is the provision of a display system whichoperates at frequencies used in home television receivers and affordsthe ability to display information moving in lines vertically across theface of the display tube, or characters moving in lines from right toleft across the face of the display tube.

Another feature of this invention is the ability to effectuate suchmotion of the data, smoothly and at different rates.

In accordance with this invention, data is called out of a memory to bedisplayed from an address which is provided by a line display counterand a character display counter. Means are provided, when it is desiredto roll the data upward, to increase the count of the line counter byone, at the end of a predetermined time whereby the data appears to bemoving upwardly.

Where it is desired that the data perform a character crawl operation,then at the end of a line of data which is displayed, the charactercounter has its residual count incremented by one rather than beingreset to zero, whereby a character which, ordinarily for example is atthe end of the line which is displayed, successively is displayed inpositions from the right side to the left side of the line.

Other features are provided for ensuring the proper blanking, avoiding ajumping" of the data, and also providing for the display of new orincoming information while in the roll or crawl mode of operation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram illustratingthe general layout of a display system wherein this invention isemployed.

FIG. 2 is a detailed block diagram of a display control unit which isemployed herein.

FIG. 3 is a block schematic diagram of the display counter controlcircuit 32.

FIG. 4 is a block schematic drawing of the X and Y-matrix counters.

FIG. 5 illustrates a character constructed at selected dots in a dotmatrix in accordance with this invention.

FIG. 6 is a block schematic of the display line and character counters.

FIG. 7 is a block schematic diagram of the cursor generator and linecharacter counters.

FIG. d is a block schematic diagram of the memory address generator.

FIGS. 9A, 9B and 9C and 9D constitute block schematic diagram of theroll and crawl circuits in accordance with this invention.

FIGS. 10 and II are schematic diagrams of logic circuits used in theinvention.

FIG. 12 is a block schematic diagram of roll and crawl loading logic.

FIG. 13 is a block schematic diagram of another arrangement forachieving roll and crawl.

FIG. M is a waveform diagram shown to assist in an understanding of thisinvention.

FIG. 15 is a block schematic diagram of a circuit used for generatinglogic signals used in the invention.

FIG. 16 is a block schematic of logic circuits used to generate theaddress-incrementing pulse.

FIG. 17 is a block schematic diagram of a circuit used to generate extrapulses for smoothing the roll operator.

FIG. 18 is a block schematic circuit of a blanking signal generator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The descriptions of FIGS. 1through 8 are substantially identical with the descriptions of FIGS. 11through 8 found in the previously indicated application for the displaysystem by Martin Kite et al. This description is. being repeated here inorder to afford a better understanding of the invention.

Referring now to FIG. 1, a general arrangement in accordance with thisinvention would comprise a standard TV monitor 10, (more than one may beused if required,) which displays human readable data. Digital data maybe entered into the system from any data source, illustrative of whichthere is shown a tape reader 112 and/or a typewriter keyboard M. Thisdata is fed into a display control unit 16 whose function it is to storethe data in a manner so that it may be properly read out for display onthe TV monitor or sent to some other utilization device 18, such askeypunch, a printout device, etc. The display control unit also includesa novel character generator which, in response to the datarepresentative code produces the video signals which are displayed asreadable data on the TV monitor 10.

FIG. 2 is a block schematic diagram illustrating details of the displaycontrol unit. A tape reader 12 or a typewriter keyboard M are wellknown, and commercially available pieces of hardware. For the purposesof this invention, and in the manner that they function normally, thetape reader produces as an output eight binary signals together with astrobe pulse, each time a character is read out. Seven of the eight bitsrepresent an alphanumeric character. The eighth bit is parity. Thekeyboard M, which can be a facsimile typewriter, also produces at itsoutput sevenbit character signals with an eighth bit having paritysignificance, together with strobe pulse. In each of these cases, thesignals are produced in parallel on eight data lines and a strobe pulseis produced on a ninth line. The signals are applied to interfacecircuits 60.

Basic operating synchronization signals for the display control unit maybe obtained from an external source of sync signals 16. This externalsync signal source may comprise either a television station syncgenerator, or a composite video signal such as may be obtained from avideotape device. Signals from either of these may be processed toprovide horizontal sync signals and vertical sync signals. If compositevideo is provided, this is applied directly to an OR-gate 18 the outputof which goes to a sync separator circuit 22. This functions inwell-known manner to separate the horizontal sync from the verticalsync. If composite video is provided by the external video signalsource, then this is applied to a video blanking circuit 20, whichconstitutes well-known circuitry for applying a blanking pulse to thecomposite video during the video interval. This leaves composite syncsignals. These are applied to the OR-gate l8 and thereafter to the syncseparator circuit to be separated into horizontal and vertical syncsignals.

The composite sync signals, which are the output of the OR- gate 18 aresupplied, at the output of the display control unit, to the TV monitorwhich is used to reproduce the video signals. The vertical sync orvertical drive pulse which is the output of the sync separator 22 isused to reset a display character counter 24, and a display line counter26, to assure that each field which is to be displayed starts properly.The display character counter has its count advanced by one for eachcharacter being displayed on a line of characters. The

display line counter 26 has its count advanced by one for each line ofcharacters which is displayed. Thus, the address of the last characterbeing displayed is always available from the output of these counters.Actual video display commences after the first 24 horizontal sync pulseswhich follow the vertical sync pulse and continues until 16 rows ofcharacter video are displayed.

There are 24 characters on each line. The first horizontal sync pulseinitiates the operation of a display counter control circuit 32. Thecounter control circuit can start a gated clock circuit 28 wherefrequency equals the picture element rate of 8 megacycles. The start ofthe operation of the gated clock is delayed, following the horizontaldrive pulse, by approximately l2 microseconds until the first characterposition in a line of characters is reached. The clock turns on and thencontinues to operate until the final character in a line is completed.Each character position is defined by a dot matrix in which only thosedots are illuminated which form a desired character. Each character usesnine dot positions along a line for the actual character display plusfive guard band positions. The total number of clock pulses generatedper line is therefore 14 times 24 (24 characters per line) or 336pulses. The clock is turned off by a clock clamp pulse at the end of aline and is turned on again at the beginning of the next line.

The display counter control also receives vertical sync pulses which areused for reset purposes. The gated clock output is used to drive anX-matrix counter 34, causing it to count through 14 counts, nine countsof which correspond to nine horizontal positions in a character dotmatrix starting from left to right, and the three further counts providefor the guard band or character spacing. The X-matrix counter 34therefore goes through a full cycle of operation for each character.Count output signals from fi to )4'1'2' are derived therefrom. Each timethe X-matrix counter completes a cycle of 12 counts, it overflows. ltsoverflow is applied to the display character counter 24 to cause it toadvance one count. The display character counter has a count capacitytotaling 24, corresponding to the number of characters displayed in eachrow. Each time the display character counter overflows, it sends theoverflow pulse back to the display counter control 32 which in turn usesthis overflow pulse, also termed a clock clamp pulse, to turn off thegated clock 28. The gated clock then waits for the next horizontal syncpulse before commencing operation again. The overflow output pulse ofthe display counter control also enables a Y-matrix counter 36 to beadvanced one count in response to the next horizontal sync pulse.

The Y-matrix counter has a total count capacity of 14 counts. Eleven ofthese are used to count the vertical dot matrix locations of acharacter. Three of these are for a guard band space between lines ofcharacters. Count outputs designated from W to Y l4 are derivedtherefrom. The overflow output of the Y-matrix counter 36 is applied tothe display line counter 26 to cause it to advance one count. Thedisplay line counter has a total count capacity of 16 corresponding tothe 16 lines of characters which are displayed in one field of thisinvention.

A character generator 38 is provided which has applied thereto the countoutputs of the X- and Y-matrix counters. In response to these, thecharacter generator generates video signals representing each one of thealphanumeric characters which the system is capable of displaying. In anembodiment of the invention which has been built and successfullyoperated, the character generated created 64 alphanumeric characters.The output of the character generator is applied to the video selector30. This functions to select, in response to a seven-bit alphanumericcode derived from the core memory 40 of the system, a specific characterfrom all of those being applied to the video selector, which characteris represented by that alphanumeric code. More specifically, the corememory 40 supplies coded signals, one character at a time to an outputregister 42, which in turn applies them to a data decoder 44 whichdecodes them successively and enables the video selector to select theproper video character signals. In addition, the video selector 30 iscapable of being modulated by a flash control circuit 46. The flashcontrol circuit contains an oscillating circuit that may be turned on bya flash code which is stored in the memory and which is a nonviewable"character. The flash control 46 remains on until either the nextfollowing horizontal drive pulse appears or a space code which separatesthe following word appears. Operation of the flash control 46 causes allcharacters of a word that are displayed thereafter to flicker and thuscall attention to itself.

After each character is displayed, an unload cycle of the core memory 40is made to occur to place the alphanumeric signals corresponding to thenext character of a row in the output register 42. The address fromwhich the character in core memory is read is provided by the countconditions of the display character counter and display line counter. Aspecific core memory address is provided for each of the 384 countswhich these counters provide. The display character counter 64 anddisplay line counter 66 have their outputs connected to a memory addressgenerator 67, which produces the address information for the core memory40.

The output of the video selector 30, which comprises the character videosignals, is applied to a mixer circuit 50 and to an output terminal 52.The mixer circuit combines character video signals with a cursor signalwhich is provided from a cursor generator 54. The cursor video signalhas approximately one-half of the intensity of the character signals.The cursor video signal indicates, on the pattern displayed on the faceof the television monitor, the corresponding character signal address inthe memory into which the next input character digital signals will beplaced when the system is in the write mode. The mixer output is appliedto an output terminal 55. In addition, composite sync signals from theoutput of the OR- gate 18 are made available at a terminal 56. Thesethree signals, namely composite sync, character video with cursor, andcharacter video without cursor, are thus available at the three outputterminals for being applied to a television monitor for display.

The tape reader 12 and the keyboard 14 have their outputs connected tothe interface circuitry 60, The interface circuitry serves to check theincoming data lines from either of the two inputs upon receipt of itsassociated data strobe presented on the strobe lines. If the data isalphanumeric data to be displayed, the input strobe signal triggers asingle load cycle of the core memory. This function is provided by thedata input control circuit 62. In the load cycle operation, the inputcharacter is loaded into the core memory at an address which isdetermined by the count outputs of the cursor character counter 64 andthe cursor line counter 66. The cursor generator 54 detects coincidencebetween the cursor counters and the display counters and causes the loadoperation to occur when these counters have the same count. Aspreviously indicated, this occurs at an address in memory correspondingto the position visually indicated by the cursor on the output monitor.Thus, the load operation into the core memory occurs at a location whichcorresponds to the location of the cursor. From the foregoing it will beappreciated that the memory should provide storage for 512 alphanumericcharacters of eight bits per character.

Other signals from the interface circuit are provided in response to theincoming control codes. These specific control codes do not result in amemory load cycle but rather generate signals on appropriate lines outof the interface circuit. These lines perform such functions as cursoron-off, cursor right, cursor left, cursor new line, cursor home, cursorup, cursor down, etc. This will become more clear as this explanationprogresses.

During the write mode, as each character is loaded into the core memory,a single pulse advances the cursor character counter by one count. Whenthe cursor character counter overflows, its output advances the cursorline counter. lnput load operations therefore, cause the cursor to beadvanced character by character and line by line in a manner similar tothe typing operation of a typewriter.

The output register 42 may also be used if desired to transmit datawhich is within the memory to an external utilization device 19 such astape or a transmitter or an external printer. An end of line" or end ofmessage" circuit 69 driven by the cursor counters, may be used inconjunction with external transmission of data to signal theiroccurrences to external equipment.

DlSlPlLAY COUNTER CONTROL ClRCUlT 32 H6. 3 is a bloclt schematic diagramof the display counter control circuit. This circuit arrangementfunctions to initiate operation of the gated clock oscillator at theproper time so that the subsequent matrix and display counters maycommence to operate at the proper time and in the proper time sequence.In a television-type display both a top margin as well as a left sidemargin must be provided for. Essentially the display counter controlcircuit provides for these delays. The first vertical sync pulse whichis delivered by the output of the sync separator 22 is applied to aflip-flop 102 to drive it to its set state. This causes the Q output ofthe flip-flop to become high. The Q output of the flip-flop enables anAND-gate lltMl whereby it can pass horizontal sync pulses which arereceived from the sync separator. These are applied to drive a 24-countcounter 166. This counter provides a top margin delay. The 24th count ofthe counter is used to reset the flip-flop 1102 and sets a flip-flop1166. The next vertical sync pulse enables flipflop W2 again andsimultaneously resets the 24-count counter so it can begin countingagain.

The Q output of flip-flop 106 enables an AND-gate 110 to pass horizontalsync pulses. The output of the AND-gate 11116 is applied to a delaycircuit M2. The delay circuit provides a delay whose duration isdetermined by the size of the desired left-hand margin on the displaytube. The output of delay cir cuit 1112 sets a flip-flop 1114. The Qoutput of the flip-flop 11114, which is high in response to its setinput being enabled, is applied to the gated clock oscillator to causeit to commence to produce clock pulses.

Flip-flop 11114 is reset by a B16 output, also called a clock clamppulse, which is received from the display character counter which countsthe number of characters displayed on a line. After the last characterhas been displayed flip-flop 1114 is reset so that at the commencementof the next line, signaled by the appearance of another horizontal syncpulse, a delay is provided on the left-hand side of the display tube.The flipflop 108 is reset by a W signal which is provided by the displayline counter. This signal occurs after the last character on the lastline has been displayed. Accordingly, flip-flop 1108 cannot be set againuntil the counter W6 counted through its next 24 counts to provide thetop margin delay.

X- AND Y-MATRIX COUNTERS (Mr-36) FIG. 6 is a block schematic diagram ofthe X- and Y-dot matrix counters. A character, in accordance with thisinvention, is made by illuminating selected dots in a dot matrix thatextends nine dots in a horizontal direction and eleven dots in avertical direction. There are five dot spaces allowed between characterson a line to serve as a guard band, and three dot spaces between linesof characters, also to serve as a guard band. Thus, the counter thatcounts for the horizontal dot placement will have a count capacity of i4and the counter that counts for the vertical dot placement will have acount capacity of 14.

In FIG. 4, there is shown a horizontal counter 1116 which is made up ofsix flip-flops, respectively 1116A through llll6F. Each one of theseflip-flops is of the type known as Jli flipflop. it is well known andcommercially purchasable.

Each flip-flop has J, K and C inputs, and Q and Q outputs. When a clockpulse is applied to its C input the flip-flop will transfer to itsoutputs the state of its J and ii inputs. Thus, if the J input is highand the K input is low when a C or clock pulse is applied to the Cinput, the Q output will be high and the Q output will be low. The J andit inputs are applied to the respective flip-flops from the Q and Qoutputs of the respective flip-flops through NAND gates. A NAND gatebehaves like an AND gate followed by an inverter. Accordingly, when thetwo inputs to the NAND gate are high, its output is low and when theinputs to the NAND gate are low, its output is high. When one of theinputs is high and the other is low, the NAND gate output is high.

The counter llll6 has the Q and Q outputs of the respective flip-flops116A through 1116B respectively connected to the J and K inputs of theimmediately following flip-flops through the respective NAND-gates 117Aand 117A through 1111715 and H713. NAND-gates 1116A and 116A areconnected to the respective J and K inputs of flip-flop 1116A. The NAND-gate 1 WA has one input connected to the 6 output of flip-flop l1l6Fwhich is designated as H 6. The NAND-gate 1116 has its inputsrespectively connected to the Q outputs of respective flip-flops M612and lll6F. These Q outputs are respectively designated as H5 and H6.

It should be noted that whenever a designation is shown for only oneNAND gate input, the other input of the NAND gate is connected to a biassource 1120. As the result, a one-input NAND gate acts as an inverter toinvert the input.

The respective Q and Q outputs of flip-flops llll6A through lll6F arerespectively designated as Hll through H6 and FF through H6. These arecollected by the 112 NAND gates, respectively 1121 through 1135, toprovide 14 output count indications in their not form. These aredesignated by X ll through m. Thus, upon the occurrence of an HR and minput to NAND-gate 1211, it will produce an output designated as m,which is the first output count of the counter. H6 and H7 occurring atthe input of NAND-gate 126 produce an Y6 output, m and H6 occurringsimultaneously at the input of NAND- gate 132 produces an Yf'output or anot 12 count output.

The manner in which the counter H6 functions is for each one of theflip-flops to successively assume its one state or state with its Qoutput high and thereafter each flip-flop successively returns to thestate with its 6 output high. The counter is cyclic and will repeat thisoperation in response to successive applications or clock pulses fromthe gated clock oscillator 134. This oscillator comprises a circuitwhich, in the presence of an enabling input from flip-flop lid in FIG.3, provides successive clock pulses to the: counter H6.

To illustrate how the counter works, assume initially that all theflip-flop stages are in their zero state. The Q output of flipfiopllll6F is high. Upon the occurrence of the first clock pulse from thegated clock oscillator 1M, flip-flop 116A will be driven to its onestate with its Q output high, since itsJ input is now high and its l(input is low. Upon the occurrence of the next clock pulse, flip-flop116B assumes a one state. This progresses with successive clock pulsesuntil flip-flop ll6F assumes its one state. Since, the K input toflip-flop lll6A is driven to its high state in response to H6 and H5which are connected to the NAND-gate 118A being high, flip-flop ll6A isdriven to its zero state with its 6 output high. This zero state of thecounter lllfiA is successively passed with the occurrence of each clockpulse to all of the flip-flops in the counter. From an understanding ofthe operation of this counter, it should now be understood how theinputs to the NAND-gates 1211 through 132 operate to produce theindicated count outputs.

Counter M0 is identical in construction with counter 116. Accordingly,it can produce 14 count outputs. It advances in respect to pulsesobtained from the output of gate in FIG. 3. These are essentiallyhorizontal sync pulses. The NAND- gates Mil through 1 .50 are connectedto the flip-flop outputs for the purpose of deriving the respectivecounts one through 14 which are in their not" form. The Q and Q outputsof the respective flip-flops of the counter M6 are respectivelydesignated from V11 through V7 and from VT to W. The counter Hill, whichcounts for the vertical dot positions, is given a count capacity of 14counts. Since it is customary to reference the bottom line of acharacter as a first position and the top of a character as the lastposition, assuming each location or position ofa line were given anumber, the bottom ofa character would be considered in the Y1 locationand the top would be considered in the Yll location. Therefore, whilethe present invention displays a character .in television raster form,where the top of the character appears first and the bottom last, thecount output of the Y-matrix counter is given a reverse countdesignation. That is, the first count of the counter is designated as W,the 1 l-count of the counter is designated as H, W and W, which aregenerated when all of the stages of the counter are in their zero state,are combined to produce a Yl4 count. The reasoning for this arrangementwill become more clear with a description of FIG. 5.

FIG. 4 shows how pulse signals Y1 through W and Ti through W and W aregenerated. In addition to these signals, other logic signals arerequired for the operation of this invention. Thus, in FIG. 4, aNAND-gate 152 is used to collect m, W, m, m and W together with the Qoutput of a flip-flop 154. The Q output of the flip-flop 154 is enabledwhen a W signal is applied to its clock input. The flipflop remains setuntil the occurrence of a m signal (Y5 and Y6). This is produced whencounter 140 provides a W and W output to a NAND-gate 156. Thus,flip-flop 154 is set at the end of a counting cycle of counter 140 andis reset upon the occurrence of the l2th count output of the flip-flop140. The output of NAND-gate 152 is inverted by NAND-gate 158 to producea signal designated as PPl. The E of not 12 count of the counter 116 isinverted by a NAND-gate 160 to produce an X12 count.

EXAMPLE OF A DOT MATRIX CHARACTER FIG. 5 shows the appearance of acharacter, A, constructed to selected dots in a dot matrix in accordancewith this invention, with the appropriate designations applied to thepossible dot locations which may be used for representing a character.There may be as many as 32 of these characters displayed in a lineacross the face of the display tube. There may be as many as l6 of theselines displayed vertically. These values are given by way ofillustration of an operative embodiment of the invention which has beenbuilt, and are not to be construed as a limitation upon the invention.

DISPLAY LINE COUNTER AND DISPLAY CHARACTER COUNTER The display linecounter and the display character counter (FIG. 6) respectively 26 and24 are each the usual binary counters with respective count capacitiesof 16 and 32. Each time an 766 signal is generated by the X-matrixcounter 34, the display character counter is advanced one count. Eachtime a W signal is generated by the Y-matrix counter 36, the displayline counter is advanced one count. The display character counter hasits respective outputs designated Bl, El, B2, E, through B16, 8 16. Thedisplay line counter has its outputs designated as Wl, WT, W2, 72, W8, W8. The character counter is the one which keeps track of the number ofcharacters on a line, for which 24 are allowed. The E16 output of thecharacter counter, referring back to FIG. 3, is the output which turnsoff the gated clock oscillator. This occurs when the last character in aline has been displayed. The last output of the display line counter,which is designated as W, is the one which turns off flip-flop 108 inFIG. 3. This occurs at the end of the last line which is displayed.

CURSOR GENERATOR 54 AND COUNTERS 64, 66

The cursor Xcounter 64, as shown in FIG. 7, is a reversible counterhaving any of the well-known reversible counter constructions. Its 32outputs are respectively designated at A1, A1, through A16, KY6. Thiscounter is advanced by receiving a signal from whatever external datainput device is employed. A signal for advancing the counter is suppliedwith each character when the display control'is is in its write mode.Such a signal is supplied from the typewriter to the cursor right" inputof the counter. The counter may be made to count in reverse by receivingan input signal on its "cursor left" terminal, from the typewriterkeyboard. The cursor signal, which by way of example has been indicatedas a background display of half intensity for a character, will occur atthe proper time, at a location along a line determined by the countoutput or by the address represented by the count output of counter 64.

A cursor Y-counter, which is similar in construction and operation tothe cursor X-counter, has a l'6-count capacity and is also reversible.This counter is advanced by signals from the keyboard applied to itscursor down terminal and is caused to count backwards in response topulses received which are applied to its cursor up terminal. Thiscounter establishes, by its output, the line address on which the cursorsignal is displayed. The output of this counter is designated by Z1, iito 28,3, with the Z8 signal being the l6th or highest count output ofthe counter.

The cursor is displayed only when there is a concurrence in the addressindicated by the cursor counters and the display counters. To achievethis operation, a comparator circuit 162 compares the address outputs ofthe counter 64 and the counter 24, shown in FIG. 6, and when there is anidentity it provides an output signal to a NAND-gate 164. Another inputto this NAND gate is the PPl signal which is generated by the logicshown in FIG. 4. This PPl signal, in view of the presence of theinverter 158, (in FIG. 4), is present from in through X 9 time. From mthrough W time, the PPI signal is not present and no output is obtainedfrom NAND-gate I64. Upon the occurrence of a comparator signal and a PP]signal, a JK flip-flop 166 is driven so that its Q ou tp ut is high.This flip-flop is reset upon the occurrence of an X10 signal.

The occurrence of the cursor on a particular line is determined by theoutput of a comparator 170. This comparator compares the addressprovided by the output counts of the cursor counter 66 and the displayline counter 26. The output of the Y-comparator is applied to theNAND-gate 168. The typewriter keyboard 14 will have a key which can beoperated to actuate a circuit which can provide a voltage to a thirdinput to the NAND-gate 168 designated as the cursor on-off" input. Whenthis voltage is not present, no cursor is provided. This circuit isshown subsequently herein in FIG. 18.

Therefore, NAND-gate 168 functions to provide a cursor signal outputwhen there is a concurrence in the addresses at the outputs of thecursor X- and Y-counters and the display character and line counters.Since the display counters are sequenced continuously through theircount states, there will be concurrence of cursor and character countersonly at one location over the entire face of the display tube.Accordingly, the cursor will be displayed at one character locationonly.

The memory storage device which is employed with this embodiment of theinvention should be able to store, for readout onto the face of adisplay tube, as many characters as will be displayed across the face ofthe tube. The example given by way of illustration herein is 24x16 or384 characters, or more correctly the code bits to represent 384characters. Thus a total of at least 8X384 or 3,072 bits is required.There should be a character location in the memory which corresponds tothe location on the display tube face at which that character is to bedisplayed. The memory must be addressed successively for the purpose ofsuccessively reading out the characters for display. The successiveaddressing of the memory is a function of the display counters.

The address of a location in the memory into which data is to be enteredis indicated by the address of the cursor. This address can be changedby applying signals to the cursor counters which establish the line andthe location along the line desired for the cursor, and thereby thelocation in the memory into which data will be introduced. The cursorcounters may be advanced by actuation of the typewriter keyboard in anormal manner for the purpose of writing character by character into thememory. Provision may also be made for advancing the cursor counterswhen input of characters is from a tape reader or any other source.

MEMORY ADDRESS GENERATOR 157 FIG. 9 is a schematic representation of amemory address generator. By way of illustration, and not to serve as alimitation, a magnetic core memory was employed with an embodiment ofthis invention which was built and operated.

The memory address generator addresses the memory for the purpose ofreading out the data stored therein which is converted into videosignals and then displayed. The address generator also provides theaddress of the locations into which incoming data is stored. The displaycharacter and line counters provide the address information forinstructing the memory as to the location from which readout is tooccur. The cursor X- and Y-counters provide the address information forinstructing the memory as to the location at which data is to beentered.

As may be seen in FIG. 6, the memory address generator merely comprisesa number of gates which are connected to the outputs of the respectivedisplay and cursor counters. The set of gates connected to the displaycounters are enabled during the process of readout whereby the addresspresented to the memory is that indicated by the display counters.Altematively, the gates connected to the cursor counter are enabled whenwrite operation is desired. The outputs from the flipflops making up thedisplay character counter 2 1 are respectively applied to each one ofthe NAND-gates 171 through 175. It should be remembered that the counter24 is a binary counter and its output presents a pulse pattern in binarycode representative of one of its 32 counts. The inputs to these NANDgates are designated by the terminology B1, B2, 1841, B9 and 1316, whichcorresponds to the outputs shown for the counter 241 in FIG. 6.Similarly, the W1, W2, W1 and W9 outputs of the line counter 26 arerespectively applied to the NAND-gates 176, 177, 178 and 179.

The five outputs of the cursor character counter 64 are respectivelyapplied to the respective NAND-gates 1110, 191, 1112, 183 and 1841. Theoutputs of the cursor line counter 66 are respectively applied to therespective NAND-gates 195, 1315, 187 and 198. NAND-gate 199 receives theoutput of NAND gates 171 and 1M). NAND-gate 191) receives the output ofNAND-gates 172 and 191. NAND-gate 191 receives the output of NAND-gates1113, 182. NAND-gate 192 receives the outputs of NAND-gates 174 and1113. NAND-gate 193 receives the outputs of NAND-gates 175 and 1M. NAND-gate 194 has applied to it the outputs of NAND-gates 176 and 185.NAND-gate 195 receives the outputs of NAND-gates 177 and 1%. NAND-gate196 receives the outputs of NAND- gates 179 and 187. NAND-gate 197receives the outputs of NAND-gates 179 and 198.

An inverter 199 receives a signal from a read-write signal source 199which is actuated by the typewriter keyboard or other input data source,when it is desired to write. Otherwise, and normally, a low signal isreceived from the read-write signal source. Accordingly, the output ofinverter 199 is high when in the read mode and is low when in the writemode. The output of inverter 199 is applied to an inverter 201 as wellas to all of the NAND-gates 171 through 179. The output of inverter 201is applied to all of the NAND-gates 1911 through 1%.

In the read mode, the output of inverter 199 is high whereby theNAND-gates 171 through 179 are all enabled. The high input to inverter201 results in a low output whereby NAND- gates 130 through 188 are notenabled. Thus, the outputs of NAND-gates 189 through 197 will be theoutputs of NAND- gates 171 through 179 or the address data from thedisplay counters. in the WRITE mode of operation, a high signal isapplied to the input ofinverter 199. This is inverted, thus holdingNAND-gates 171 through 179 disabled. However, the inverter 201 willprovide a high or enabling input to the NAND-gates 181) through 198. Asa result the NAND-gates 1119 through 197 will provide an address to thememory which constitutes the count outputs of the two cursor counters.

SUMMARY OF ROLL OPERATKON In the vertical roll operation the datadisplayed on the face of the cathode-ray tube appears to roll upward asnew information is entered from the bottom. The top and bottom characterrow positions are blanked out giving the effect of rows of dataappearing gradually from behind a mask at the bottom and graduallydisappearing behind a mask at the top. New data is written into memoryduring the time the address of data would be displayed in the area thatis blanked. Provision is made for several roll speeds. Choice of speeddepends on capabilities of the data source which feeds new data to bedisplayed and visual effect desired.

The circuitry provided achieves the indicated effects by blanking thefirst and last line positions on the display tube, and by periodicallyincrementing the count of the display character counter by one beforethe commencement of the first line to be displayed in the succeedingfield. In order to avoid the appearance of jumping, provision is alsomade for delaying the start of the first line to be displayed byintervals ranging for the interval of 14 horizontal sync pulses, down toone sync-pulse interval, and thereafter repeating the cycle from 14 toone again. The speed of display is handled by varying the rate of changeof the amount that the first line of display is delayed.

HORIZONTAL CRAWL in horizontal crawl a single row of characters may bemade to appear from the right side of the screen and crawl graduallyacross the screen from right to left, disappearing at the left. Theextreme leftand right-hand character column position are blankedproducing a curtain, from which characters appear from the right andinto which they disappear on the left. New data is entered during a timea memory address would be displayed in the blanked area. Provision ismade for three crawl speeds, choice depending on the capabilities of thedata source and the visual effect desired.

The accomplishment of the crawl is done in a somewhat similar manner tothe accomplishment of the roll. The character display counter whichestablishes the address in the memory from which a readout occurs hasits starting count incremented by one periodically before the beginningof the display of the first line in a field. Provision is made fordelaying the start of a line, first 14 clock pulses, then 13, etc. anddown to one, and then starting back at 14 again. Crawl speed may bevaried by changing the rate at which the delay is changed.

ROLL OPERATION Referring now to FIGS. 9A, 9B, 9C and 90, there may beseen block schematic diagrams of the apparatus for forming the roll andcrawl operation.

In order to initiate operation, a roll key 200 is depressed at thetypewriter keyboard. Also, either a slow roll key 202, a slow range key203, or a fast roll key 204, may be depressed as determined by the speedof the roll desired. When none of these keys is depressed, the rollspeed is between that of slow and fast roll. Depressing the roll key 200causes a flip-flop 206 to be set, upon the occurrence of the nextvertical sync pulse, (It E1), which is applied to its clock inputterminal. When it is no longer desired to have the roll operation, theroll key is opened. An inverter 209, which is connected to the resetinput of the flip-flop 206, applies an input such that flip-flop 206will be reset at the next vertical sync pulse.

When flip-flop 206 is set, its output is applied first to an inverter210, whose output provides a W DC level, then directly to an outputterminal whose output provides a VR DC level, and then to a NAND-gate214, which causes its output to go from low to high, indicative ofeither VR of HC (horizontal crawl).

In the vertical roll mode, as well as in the horizontal crawl mode,since the line and character display counters 26 and 24 will be operatedin a manner so that they are not reset and at the beginning of eachsuccessive display field the counters will not have a beginning count,in order to provide the necessary we and W signals to the flip-flop 108and 114, shown in FIG. 3, a substitute row and column counter 216 isemployed. When in the roll mode, the output of this counter is providedwhen it attains the count of 16. When in the crawl mode, the output ofthis counter is used when it attains the count of 24.

When the VR signal goes high, then a NAND-gate 218 can apply pulses,designated as W, to drive the substitute Row 1 column counter 216. TheW4 pulses are derived from a oneshot circuit 220 which is driven inresponse to W pulses. It will be recalled that the Y 14 pulses arederived from the output of the Y-character matrix counter.

The substitute row-column counter 216, when it reaches the count of 16,provides an output to an AND-gate 222. This AND gate has as its secondrequired input the VR output of the flip-flop 206. It will be noted thatanother AND-gate 224 is blocked at this time, since one of its requiredinputs W is low. The other input to this AND-gate 224 is the regular W 8output from the display line counter 26. Therefore, when the system isnot in the roll mode, the W6 output causes an output from the AND gatewhich is connected to an OR-gate 226. The AND-gate 222 is also connectedto this OR-gate 226. The output of the OR gate is a W signal. This isthe signal which is applied to flip-flop 108 to cause it to resetwhereby the gated clock oscillator, which drives the X-counter 1 16 isterminated, and horizontal sync pulses are no longer applied to advancethe Y-counter 140.

From the foregoing, it should be appreciated why the counter 216 isdesignated as a substitute row-column counter. In the roll mode, or inthe crawl mode, as will be seen later, its output is substituted for theline counter or the character counter for the purpose of keeping trackof the number of lines or characters which have been displayed, but notfor the purpose of addressing the memory for readout.

Referring back to the one-shot 220, it will be seen that its output Yl4* is also applied to an AND-gate 230. Another input to this gate isVR. The third required input to this gate, which enables it to apply apulse to the display line counter, increasing its count by one, is anRS2 pulse. The output of gate 230 to the display line counter is inaddition to the regular flow of Yl4 pulses which advance the countercount by 16. It occurs each time an RS2 signal occurs and causes theroll effect. How the RS2 signal is derived will be describedsubsequently. At this point it should suffice to state that an RS2 pulseis generated immediately upon going into a roll or a crawl mode ofoperation, and also after predetermined intervals as determined by theroll or crawl speed selected.

Aside from the time the RS2 pulse is provided, the display line counteradvances in its normal manner in response to the W pulses. Accordingly,at the end of a predetermined number of display fields in the roll mode,the display line counter ends up with a one count. Another count isadded by the application of a W" pulse. Thus, at the beginning of thenext display field, the third line of data in the register will bedisplayed. After the next predetermined number of display fields haveoccurred, another WP pulse is applied to the counter and the fourth dataline in the memory will be shown at the top of the display field.

The foregoing operation gives the displayed data the appearance ofrolling upward across the face of the display tube. The substituterow-column counter 216 provides the necessary Wi" pulse at the end ofthe l6th display line which is applied to the clock control in FIG. 3,at the right time, despite the face that the regular display linecounter provides the W8 pulses at the wrong time.

Blanking signals for blanking out the top and bottom lines is providedby structure which will be described subsequently herein.

From the structure described thus far, while the roll effect isprovided, it is not very smooth and gives the appearance of jumping upthe space by one line. The roll effect can be made much smoother bydividing up the increment of one line into smaller increments of motion.That is, by starting the top line being displayed down the distance ofl4 scan lines with the rest of the display following thereafter, thendisplaying the next top line for the next display 13 scan lines, then12, etc., returning again to 14 after there has been a one-scan-linedelay, the roll mode of display is made smooth.

This operation is achieved by inhibiting a certain number of clockpulses from the Y-counter, and gradually decreasing the number of clockpulses withheld from the Y-counter for each field being displayed, inthe manner previously described.

Now if the clock pulses are withheld from the Y-counter for the intervalrequired for 14 scan lines to occur, the display that would follow wouldbe displaced down by 14 scan lines or one row and the data that would bedisplayed at that time would be the line of data that would otherwisehave been displayed in the preceding row. However, the W pulse adds acount to the counter to ensure that the line displayed is the properone. The line that would have been displayed is now the bottom line anddoes not appear.

The indicated delay of clock pulses is produced simply by counting theI-ICP pulses (horizontal clock pulses) and after a certain number ofthem, which are counted by a counter, a flip-flop is reset which in turnallows the HCP pulses to be applied to the Y-counter. A delay counter232 counts 14 HCP pulses and then resets a flip-flop 234 with itsoutput. The set output of the flip-flop is applied to two NAND-gatesrespectively 236 and 238. NAND-gate 236 requires as its other input a VRsignal. A following NAND-gate 240 is inhibited in the presence of anoutput from the NAND-gate 236. The other input to the NAND-gate 240 isan input from an inverter 242, which is driven in response to horizontalclock pulses which are received from the NAND-gate in FIG. 3. The outputof the NAND-gate 240, when it is enabled, constitutes the clock pulseswhich drive the Y-counter shown in FIG. 4.

The delay counter 232 establishes the amount of delay until clock pulsesare applied to the Y- (or X- counters. Control of the variation in suchdelay is achieved by changing the count of the delay counter so that ithas a different value each time it starts counting to establish theamount of the delay. Establishment of the initial count of the counteris achieved by a delay reference counter 242. The delay referencecounter count is transferred into the delay counter through transfergates, which are enabled during the vertical retrace period. The countin the delay reference counter is established in response to amultivibrator 246 output. The multivibrator is under the control of aprogrammable counter 248 and associated logic 250, designated as countercontrol gates.

The variable delay interval provides an opportunity to obtain speedcontrol since, the more rapidly the delay is decreased the more quicklythe display appears to move. Accordingly, provision is made for countingthrough the delay interval at different rates in accordance with signalsderived by depressing the slow roll key 202 or fast roll key 204.

The slow roll key 202 output is applied to a NOR-gate 252 to which theslow crawl key 254 output is also applied. The output of the NOR-gate252 is applied, to an inverter 258 whose output is connected to the setinput of the flip-flop 256, and also to the reset input of the flip-flop256. The application of the W signal to the clock input terminal of theflip-flop 256 enables it to be reset whereby its output is an S signal.Otherwise its output is an signal. The fast roll key 204 and a fastcrawl key 260 are connected to a NOR-gate 262. The output of theNOR-gate is connected directly to the reset input of a flip-flop 264 andalso through an inverter 266 to the set input of the flip-flop. Theapplication of the W signal to the clock terminal of the flip-flop, inthe presence of a fast roll or

1. In a continuous data display system of the type wherein a memory stores data in the form of characters in predetermined lines of characters and there is a means for addressing said memory for reading characters out of said memory at a time so that they are displayed at locations on the face of a continuously scanned display system corresponding to the locations in said memory, means for providing a continuously moving effect to the data being displayed comprising: means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system, and means for applying said address-incrementing signal to said means for addressing said memory for Reading a character out of said memory at a time to be displayed by said continuously scanning display system at a location displaced from the location of the character in said memory.
 2. In a continuous display system as recited in claim 1 wherein there is provided a means for blanking the first and last display line locations of said continuously scanning display system and the characters read out of said memory by said means for addressing said memory are displaced to line locations which are different than the line locations in memory from which they are read out.
 3. In a continuous display system as recited in claim 1 wherein there is provided a means for blanking the first and last character position of each display line of said continuously scanning display system and the characters read out of said memory by said means for addressing said memory are displaced to locations along a line which are different than the line locations in memory from which they are read out.
 4. In a continuous data display system as recited in claim 2 wherein there is included means for recurrently and successively delaying a display of lines of data on said display device face by varying intervals of time until a predetermined interval has been reached.
 5. In a continuous data display system as recited in claim 3 wherein there is included means for recurrently and successively delaying a display of characters of data on each line of data on said display device face by decreasing intervals of time until a predetermined interval has been reached.
 6. In a continuous data display system of the type wherein a memory stores data in the form of characters and there is provided means for displaying said characters on the face of a continuously scanned display tube at address locations corresponding to those in memory, said means for displaying including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line, first means for altering the count in said line counter means in synchronism with the display of lines of data by said display device, second means for altering the count of said character counter in synchronism with the display of characters along a line by said display device, and read means responsive to the counts of said line counter means and said character counter means for addressing said memory for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory, means for providing a continuously moving effect to the data being displayed comprising: means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system, and means for applying said address-incrementing signal to one of said line and character counter means to cause the readout of characters from said memory by said read means at a time to be displayed at a location by said continuously scanning display system which is displaced from the location in said memory.
 7. In a continuous data display system as recited in claim 6 wherein there is provided a delay means for recurrently and successively delaying the initiation of operation of one of said first and second means for altering the count for decreasing intervals of time until a predetermined minimum interval has been attained for delaying the display by said display device and thereby preventing a jumpy display appearance.
 8. In a continuous data display system as recited in claim 6 wherein there is provided a means for blanking the first and last display line locations of said continuously scanning display system and the characters read out of said memory are displayed by said display system on line locations which are displaced from the line locations of readout from memory.
 9. In a continuous data display system as recited in claim 6 wherein there is provided a means for blanking The first and last character position of each display line of said continuously scanning display system and the characters read out of said memory are displayed at locations along a line which are different than the line locations in memory from which they are read.
 10. In a continuous display system as recited in claim 6 wherein said means for periodically generating an address-incrementing signal in synchronism with said continuously scanning display system includes delay reference counter means, means for periodically incrementing the count of said delay reference counter means by a predetermined amount in synchronism with said continuously scanning display, and means responsive to said delay reference counter means recycling from a full count to an initial count for generating an address-incrementing signal.
 11. In a continuous display system as recited in claim 7 wherein said delay means includes a delay reference counter means, means for periodically incrementing the count of said delay reference counter means by a predetermined amount in synchronism with said continuously scanning display, a delay counter means, means for continuously advancing the count of said delay counter means in synchronism with said continuously scanning display, means for entering the count in said delay reference counter means as an initial count into said delay counter means in synchronism with said continuously scanning display, and means for initiating the operation of one of said first and second counter means responsive to output from said delay counter means when it has a full count.
 12. In a continuous display system as recited in claim 6 wherein there is included a means for generating repetitively, recurrently and in synchronism with said display, delay signals having delay intervals varying from a predetermined maximum to a minimum value, and means for delaying the start of operation of said second means for altering the count of said character counter means in response to each of said delay signals to thereby prevent a jumpy display.
 13. In a continuous display system as recited in claim 6 wherein there is included a means for generating repetitively, recurrently and in synchronism with said display, delay signals having delay intervals varying from a predetermined maximum to a minimum value, and said first means for altering the count of said line counter means in response to each of said delay signals to thereby prevent a jumpy display.
 14. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster, a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line, first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals, second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals, display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and read means responsive to the counts of said line counter means and said character counter means for readiNg characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory, means for providing a continuously moving effect to the data being displayed comprising: delay reference counter means, means for periodically incrementing the count of said delay reference counter means by a predetermined amount for each vertical sync signal, means responsive to said delay reference counter means attaining a full count for generating an address-incrementing signal, and means for applying said address-incrementing signal to said line counter means to increment its address to cause readout of characters from said memory at a time to be displayed on a line location which is different from the line location in memory.
 15. In a continuous data display system as recited in claim 14 wherein said means for periodically incrementing the count of said delay reference counter means includes a programmable counter means, means for establishing the count capacity of said programmable counter means, means for applying pulses to be counted to both said programmable counter means and said delay reference counter means in response to a vertical sync pulse, and means for terminating the application of pulses by said means for applying pulses responsive to said programmable counter means attaining a full count.
 16. In a continuous data display system as recited in claim 14 wherein there is included means for delaying the application of pulses by said first means for applying pulses for altering the count in said line counter means, said means comprising a delay counter means, means for transferring the count of said delay reference counter means into said delay counter means in response to each vertical sync pulse, means for applying pulses responsive to horizontal sync pulses to said delay counter to cause it to increase its count, and means responsive to said delay counter means attaining a full count for enabling the application of pulses by said first means for applying pulses to said line counter means.
 17. In a continuous data display system as recited in claim 14 wherein there is included a means for blanking the first and last line positions of said display device including: a blanking counter means having the same count capacity as said delay counter means, means for applying pulses responsive to horizontal sync pulses to said blanking counter to advance its count, flip-flop means having a first state during which it produces a blanking signal output and a second state during which it does not produce an output, means responsive to said blanking counter means attaining its full count for driving said flip-flop means to its second state, substitute row-column counter means for indicating a count of the number of lines of data which are being displayed on said display device face, and means responsive to said substitute row-column counter means indicating the count of the last display line of data on said display device face for driving said flip-flop means to its first state.
 18. In a continuous display system as recited in claim 17 wherein there is included means for alternately writing data from a data source into memory during the blanking of the last line of data on said display device face or writing null signals into said memory during said blanking of the last line.
 19. In a continuous display system as recited in claim 17 wherein there is included means for sensing an insufficient data flow into said memory and producing a pause signal, and means responsive to said pause signal to hold further operation of said delay reference counter and delay counter until said pause signal terminates.
 20. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical Sync signals for each frame of a scanning raster, a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line, first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals, second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals, display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory, means for providing a continuously moving effect to the data being displayed comprising: delay reference counter means, means for periodically incrementing the count of said delay reference counter means by a predetermined amount for each horizontal sync signal, means responsive to said delay reference counter means attaining a full count for generating an address-incrementing signal, and means for applying said address-incrementing signal to said character counter means to increment its address to cause readout of characters from said memory at a time to be displayed on a line location which is different from the line location in memory.
 21. In a continuous data display system as recited in claim 20 where said means for periodically incrementing the count of said delay reference counter means includes a programmable counter means, means for establishing the count capacity of said programable counter means, means for generating clock pulse signals in response to horizontal and vertical sync signals, means for applying said clock pulses to be counted to both said programmable counter means and said delay reference counter means, and means for terminating the application of pulses by said means for generating clock pulses responsive to said programmable counter means attaining a full count.
 22. In a continuous data display system as recited in claim 20 wherein there is included means for delaying the application of pulses by said first means for applying pulses for altering the count in said character counter means, said means comprising a delay counter means, means for transferring the count of said delay reference counter means into said delay counter means in response to each horizontal sync pulse, means for applying said clock pulses to said delay counter to cause it to increase its count, and means responsive to said delay counter means attaining a full count for enabling the application of pulses by said first means for applying pulses to said character counter means.
 23. In a continuous data display system as recited in claim 20 wherein there is included a means for blanking the first and last character positions on each line displayed by said display device including: a blanking counter means having the same count capacity as said delay counter means, means for applying clock pulses to said blanking counter to advance its count, flip-flop means having a first state during which it produces a blanking signal output and a second state during which it does not produce an output, means responsive to said blanking counter means attaining its full count for driving said flip-flop means to its second state, substitute row-column counter means for indicating a count of the number of characters of data which are being displayed on each line on said display device face, and means responsive to said substitute row-column counter means indicating the count of the last character on a line of data on said display device face for driving said flip-flop means to its first state.
 24. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster, a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line counter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line, first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals, second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals, display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory, means for providing a continuously moving effect to the data being displayed comprising: counter means, means responsive to a vertical sync signal to enable the application of horizontal sync signals to said counter means, to be counted thereby, means responsive to a predetermined count of said counter means to generate an extra count signal, and means for applying said extra count signal to said line counter means to thereby cause the readout of a character from said memory at a time to be displayed on a line location different than the location in memory.
 25. In a continuous data display as recited in claim 24 including means responsive to said vertical sync signals for generating successive delay signals cyclically varying from predetermined minimum to maximum delay intervals, a source of high-frequency pulses at a frequency higher than said horizontal sync frequency, gate means responsive to said successive delay signals for applying high-frequency pulses from said source to said display delay counter means over the interval of each said delay signal to alter the time of commencement of each display to thereby prevent a jumpy display.
 26. In a continuous data display system of the type which operates to provide a scanning raster on the face of a display device in response to horizontal sync signals being provided for each line of a scanning raster and vertical sync signals for each frame of a scanning raster, a memory stores data in the form of characters at address locations corresponding to address locations on the face of said display device on which they are displayed in the form of lines of data, and there is provided a means synchronized by said vertical and horizontal sync signals for reading characters out of said memory to be displayed on the face of said display device, said means for reading including line coUnter means for indicating the line address of a character, a character counter means for indicating the address of a character along a line, first means for applying pulses altering the count in said line counter means synchronized by said horizontal sync signals, second means for applying pulses for altering the count in said character counter means synchronized by said horizontal sync signals, display delay counter means responsive to the occurrence of a vertical sync signal and horizontal sync signals for delaying the application of pulses by said first and second means to said respective line and character counter means until it has reached its full count capacity, and read means responsive to the counts of said line counter means and said character counter means for reading characters out of said memory for display at locations on the face of said display device corresponding to locations in said memory, means for providing a continuously moving effect to the data being displayed comprising means responsive to said horizontal sync signals for generating successive delay signals cyclically varying from predetermined maximum to predetermined minimum delay intervals, means responsive to a delay signal for generating an extra count pulse, and means for applying said extra count pulse to said character counter means to thereby cause readout of a character from said memory at a time to be displayed at a different location along a line than the one in memory.
 27. In a continuous data display as recited in claim 26 including means responsive to a delay signal to delay operation of said second means for applying pulses for the interval of said delay signal, to thereby alter the time of commencement of the display of a line of characters to avoid a jumpy display. 